High-Speed Performance, Power and Thermal Co-simulation For SoC Design

This dissertation presents a multi-faceted effort at developing standard System Design Language based tools that allow designers to the model power and thermal behavior of SoCs, including heterogeneous SoCs that include non-digital components. The research contributions made in this dissertation include: • SystemC-based power/performance co-simulation for the Intel XScale microprocessor. We performed detailed characterization of the power dissipation patterns of a variety of system components and used these results to build detailed power models, including a highly accurate, validated instruction-level power model of the XScale processor. We also proposed a scalable, efficient and validated methodology for incorporating fast, accurate power modeling capabilities into system description languages such as SystemC. This was validated against physical measurements of hardware power dissipation. • Modeling the behavior of non-digital SoC components within standard System Design Languages. We presented an approach for modeling the functionality, performance, power, and thermal behavior of a complex class of non-digital components — MEMS microhotplate-based gas sensors — within a SystemC design framework. The components modeled include both digital components (such as microprocessors, busses and memory) and MEMS devices comprising a gas sensor SoC. The first SystemC models of a MEMS-based SoC and the first SystemC models of MEMS thermal behavior were described. Techniques for significantly improving simulation speed were proposed, and their impact quantified. • Vertically Integrated Execution-Driven Power, Performance and Thermal Co-Simulation For SoCs. We adapted the above techniques and used numerical methods to model the system of differential equations that governs on-chip thermal diffusion. This allows a single high-speed simulation to span performance, power and thermal modeling of a design. It also allows feedback behaviors, such as the impact of temperature on power dissipation or performance, to be modeled seamlessly. We validated the thermal equation-solving engine on test layouts against detailed low-level tools, and illustrated the power of such a strategy by demonstrating a series of studies that designers can perform using such tools. We also assessed how simulation and accuracy are impacted by spatial and temporal resolution used for thermal modeling

Instruction-Level Power Dissipation in the Intel XScale Embedded Microprocessor

We present an instruction-level power dissipation model of the Intel XScale R° microprocessor. The XScale implements the ARMTMISA, but uses an aggressive microarchitecture and a SIMD Wireless MMXTMco-processor to speed up execution of multimedia workloads in the embedded domain. Instruction-Level power modelling was ¯rst proposed by Tiwari et. al. in 1994. Adaptations of this model have been found to be applicable to simple ARM processors. Research also shows that instructions can be clustered into groups with similar energy characteristics. We adapt these methodologies to the significantly more complex XScale processor. We characterize the processor in terms of the energy costs of opcode execution, operand values, pipeline stalls etc. through accurate measurements on hardware. This instruction-based (rather than microarchitectural) approach allows us to build a high-speed power-accurate simulator that runs at MIPS-range speeds, while achieving accuracy better than 5%. The processor core accounts only for a portion of overall power consumption, and we move beyond the core to explore the issues involved in building a SystemC simulation framework that models power dissipation of complete systems quickly, flexibly and accurately

Modeling Heterogeneous SoCs with SystemC: A Digital/MEMS Case Study

Designers of SoCs with non-digital components, such as analog or MEMS devices, can currently use high-level system design languages, such as SystemC, to model only the digital parts of a system. This is a significant limitation, making it difficult to perform key system design tasks — design space exploration, hardware-software co-design and system verification — at an early stage. This paper describes lumped analytical models of a class of complex non-digital devices — MEMS microhotplates — and presents techniques to integrate them into a SystemC simulation of a heterogeneous System-on-a-Chip (SoC). This approach makes the MEMS component behavior visible to a full-system simulation at higher levels, enabling realistic system design and testing. The contributions made in this work include the first SystemC models of a MEMS-based SoC, the first modeling of MEMS thermal behavior in SystemC, and a detailed case study of the application of these techniques to a real system. In addition, this work provides insights into how MEMS device-level design decisions can significantly impact system level behavior; it also describes how full-system modeling can help detect such phenomena and help to address detected problems early in the design flow

A Retargetable Optimizing Java-to-C Compiler for Embedded Systems

Title of Thesis: "A Retargetable Optimizing Java-to-C Compiler for Embedded Systems" Degree candidate: Ankush Varma Degree and year: Master of Science, 2003

Instruction-Level Power Dissipation in the Intel XScale

We present an instruction-level power dissipation model of the Intel XScale R # microprocessor. The XScale implements the ARM ISA, but uses an aggressive microarchitecture and a SIMD Wireless MMX co-processor to speed up execution of multimedia workloads in the embedded domain

Electrostatic Discharge Protection For Embedded-Sensor Systems-On-A-Chip

The robustness of Embedded-Sensor (ES) System-on-a-Chip (SoC) applications involves several unique design constraints. For example, space-efficient Electrostatic Discharge (ESD) protection for the CMOS devices must be provided during the sensor micromachining processes in addition to the protection provided during normal operation and handling. In this paper, reliable and space-optimized on-chip ESD protection structures are demonstrated for MicroElectroMechanical Systems (MEMS)-based ES-SoCs. This ESD protection solution involves design of novel thyristor-type devices implemented in the standard CMOS technology. Transmission Line Pulsing (TLP) measurements are presented to illustrate the thyristor-type device feasibility for I/O pads and internal sensing film electrodes ESD protection without latch-up problem

Modeling Heterogeneous SoCs with SystemC: A Digital/MEMS Case Study

Designers of SoCs with non-digital components, such as analog or MEMS devices, can currently use high-level system design languages, such as SystemC, to model only the digital parts of a system. This is a significant limitation, making it difficult to perform key system design tasks — design space exploration, hardware-software co-design and system verification — at an early stage. This paper describes lumped analytical models of a class of complex non-digital devices — MEMS microhotplates — and presents techniques to integrate them into a SystemC simulation of a heterogeneous System-on-a-Chip (SoC). This approach makes the MEMS component behavior visible to a full-system simulation at higher levels, enabling realistic system design and testing. The contributions made in this work include the first SystemC models of a MEMS-based SoC, the first modeling of MEMS thermal behavior in SystemC, and a detailed case study of the application of these techniques to a real system. In addition, this work provides insights into how MEMS device-level design decisions can significantly impact systemlevel behavior; it also describes how full-system modeling can help detect such phenomena and help to address detected problems early in the design flow